Computer Organization and Design MIPS Edition

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Computer Organization and Design: The Hardware/Software Interface, Sixth Edition, the leading, award-winning textbook from Patterson and Hennessy used by more than 40,000 students per year, continues to present the most comprehensive and readable introduction to this core computer science topic. Improvements to this new release include new sections in each chapter on Domain Specific Architectures (DSA) and updates on all real-world examples that keep it fresh and relevant for a new generation of students.

Covers parallelism in-depth, with examples and content highlighting parallel hardware and software topics
Includes new sections in each chapter on Domain Specific Architectures (DSA)
Discusses and highlights the "Eight Great Ideas" of computer architecture, including Performance via Parallelism, Performance via Pipelining, Performance via Prediction, Design for Moore's Law, Hierarchy of Memories, Abstraction to Simplify Design, Make the Common Case Fast and Dependability via Redundancy

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Front Cover 2
Computer Organization and Design 7
Copyright Page 8
Contents 11
Preface 17
1 Computer Abstractions and Technology 26
- 1.1 Introduction 27
- 1.2 Seven Great Ideas in Computer Architecture 34
- 1.3 Below Your Program 37
- 1.4 Under the Covers 40
- 1.5 Technologies for Building Processors and Memory 48
- 1.6 Performance 52
- 1.7 The Power Wall 64
- 1.8 The Sea Change: The Switch from Uniprocessors to Multiprocessors 67
- 1.9 Real Stuff: Benchmarking the Intel Core i7 70

Front Cover 2
Computer Organization and Design 7
Copyright Page 8
Contents 11
Preface 17
1 Computer Abstractions and Technology 26
- 1.1 Introduction 27
- 1.2 Seven Great Ideas in Computer Architecture 34
- 1.3 Below Your Program 37
- 1.4 Under the Covers 40
- 1.5 Technologies for Building Processors and Memory 48
- 1.6 Performance 52
- 1.7 The Power Wall 64
- 1.8 The Sea Change: The Switch from Uniprocessors to Multiprocessors 67
- 1.9 Real Stuff: Benchmarking the Intel Core i7 70
- 1.10 Going Faster: Matrix Multiply in Python 73
- 1.11 Fallacies and Pitfalls 74
- 1.12 Concluding Remarks 77
- 1.14 Self-Study 79
- 1.13 Historical Perspective and Further Reading 80
- 1.15 Exercises 97
2 Instructions: Language of the Computer 104
- 2.1 Introduction 106
- 2.2 Operations of the Computer Hardware 107
- 2.3 Operands of the Computer Hardware 110
- 2.4 Signed and Unsigned Numbers 117
- 2.5 Representing Instructions in the Computer 124
- 2.6 Logical Operations 131
- 2.7 Instructions for Making Decisions 134
- 2.8 Supporting Procedures in Computer Hardware 140
- 2.9 Communicating with People 150
- 2.10 MIPS Addressing for 32-Bit Immediates and Addresses 156
- 2.11 Parallelism and Instructions: Synchronization 165
- 2.12 Translating and Starting a Program 167
- 2.13 A C Sort Example to Put It All Together 176
- 2.14 Arrays versus Pointers 185
- 2.16 Real Stuff : ARMv7 (32-bit) Instructions 189
- 2.15 Advanced Material: Compiling C and Interpreting Java 190
- 2.17 Real Stuff : ARMv8 (64-bit) Instructions 219
- 2.18 Real Stuff : RISC-V Instructions 220
- 2.19 Real Stuff : x86 Instructions 221
- 2.20 Going Faster: Matrix Multiply in C 230
- 2.21 Fallacies and Pitfalls 231
- 2.22 Concluding Remarks 233
- 2.24 Self Study 236
- 2.23 Historical Perspective and Further Reading 237
- 2.25 Exercises 248
3 Arithmetic for Computers 259
- 3.1 Introduction 261
- 3.2 Addition and Subtraction 261
- 3.3 Multiplication 266
- 3.4 Division 272
- 3.5 Floating Point 279
- 3.6 Parallelism and Computer Arithmetic: Subword Parallelism 305
- 3.7 Real Stuff : Streaming SIMD Extensions and Advanced Vector Exten-sions in x86 307
- 3.8 Going Faster: Subword Parallelism and Matrix Multiply 308
- 3.9 Fallacies and Pitfalls 310
- 3.10 Concluding Remarks 314
- 3.12 Self Study 318
- 3.11 Historical Perspective and Further Reading 319
- 3.13 Exercises 331
4 The Processor 337
- 4.1 Introduction 339
- 4.2 Logic Design Conventions 343
- 4.3 Building a Datapath 346
- 4.4 A Simple Implementation Scheme 354
- 4.5 A Multicycle Implementation 368
- 4.6 An Overview of Pipelining 389
- 4.7 Pipelined Datapath and Control 402
- 4.8 Data Hazards: Forwarding versus Stalling 419
- 4.9 Control Hazards 432
- 4.10 Exceptions 441
- 4.11 Parallelism via Instructions 448
- 4.12 Putting It All Together: The Intel Core i7 6700 and ARM Cortex-A53 462
- 4.13 Going Faster: Instruction-Level Parallelism and Matrix Multiply 470
- 4.14 Advanced Topic: An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and Mor 473
- 4.15 Fallacies and Pitfalls 503
- 4.16 Concluding Remarks 504
- 4.18 Self-Study 505
- 4.17 Historical Perspective and Further Reading 506
- 4.19 Exercises 512
5 Large and Fast: Exploiting Memory Hierarchy 530
- 5.1 Introduction 532
- 5.2 Memory Technologies 536
- 5.3 The Basics of Caches 541
- 5.4 Measuring and Improving Cache Performance 556
- 5.5 Dependable Memory Hierarchy 576
- 5.6 Virtual Machines 582
- 5.7 Virtual Memory 586
- 5.8 A Common Framework for Memory Hierarchy 612
- 5.9 Using a Finite-State Machine to Control a Simple Cache 619
- 5.10 Parallelism and Memory Hierarchies: Cache Coherence 624
- 5.11 Parallelism and Memory Hierarchy: Redundant Arrays of Inexpensive Disks 629
- 5.12 Advanced Material: Implementing Cache Controllers 636
- 5.13 Real Stuff : The ARM Cortex-A8 and Intel Core i7 Memory Hierarchies 652
- 5.14 Going Faster: Cache Blocking and Matrix Multiply 657
- 5.15 Fallacies and Pitfalls 659
- 5.16 Concluding Remarks 663
- 5.18 Self-Study 664
- 5.17 Historical Perspective and Further Reading 665
- 5.19 Exercises 686
6 Parallel Processors from Client to Cloud 704
- 6.1 Introduction 706
- 6.2 The Difficulty of Creating Parallel Processing Programs 708
- 6.3 SISD, MIMD, SIMD, SPMD, and Vector 713
- 6.4 Hardware Multithreading 720
- 6.5 Multicore and Other Shared Memory Multiprocessors 723
- 6.6 Introduction to Graphics Processing Units 728
- 6.7 Domain Specific Architectures 735
- 6.8 Clusters, Warehouse Scale Computers, and Other Message-Passing Multiprocessors 738
- 6.9 Introduction to Multiprocessor Network Topologies 743
- 6.10 Communicating to the Outside World: Cluster Networking 747
- 6.11 Multiprocessor Benchmarks and Performance Models 756
- 6.12 Real Stuff : Benchmarking the Google TPUv3 Supercomputer and an NVIDIA Volta GPU Cluster 766
- 6.13 Going Faster: Multiple Processors and Matrix Multiply 775
- 6.14 Fallacies and Pitfalls 778
- 6.15 Concluding Remarks 781
- 6.17 Self Study 783
- 6.16 Historical Perspective and Further Reading 784
- 6.18 Exercises 797
Appendix A. Assemblers, Linkers, and the SPIM Simulator 811
- A.1 Introduction 812
- A.2 Assemblers 819
- A.3 Linkers 827
- A.4 Loading 828
- A.5 Memory Usage 829
- A.6 Procedure Call Convention 831
- A.7 Exceptions and Interrupts 842
- A.8 Input and Output 847
- A.9 SPIM 849
- A.10 MIPS R2000 Assembly Language 854
- A.11 Concluding Remarks 890
- A.12 Exercises 891
Appendix B. The Basics of Logic Design 893
- B.1 Introduction 894
- B.2 Gates, Truth Tables, and Logic Equations 895
- B.3 Combinational Logic 900
- B.4 Using a Hardware Description Language 911
- B.5 Constructing a Basic Arithmetic Logic Unit 917
- B.6 Faster Addition: Carry Lookahead 929
- B.7 Clocks 939
- B.8 Memory Elements: Flip-Flops, Latches, and Registers 941
- B.9 Memory Elements: SRAMs and DRAMs 949
- B.10 Finite-State Machines 958
- B.11 Timing Methodologies 963
- B.12 Field Programmable Devices 969
- B.13 Concluding Remarks 970
- B.14 Exercises 971
Index 980
Appendix C. Graphics and Computing GPUs 1006
- C.1 Introduction 1007
- C.2 GPU System Architectures 1011
- C.3 Programming GPUs 1016
- C.4 Multithreaded Multiprocessor Architecture 1029
- C.5 Parallel Memory System 1040
- C.6 Floating-point Arithmetic 1045
- C.7 Real Stuff: The NVIDIA GeForce 8800 1050
- C.8 Real Stuff: Mapping Applications to GPUs 1059
- C.9 Fallacies and Pitfalls 1076
- C.10 Concluding Remarks 1080
- C.11 Historical Perspective and Further Reading 1081
Appendix D. Mapping Control to Hardware 1088
- D.1 Introduction 1089
- D.2 Implementing Combinational Control Units 1090
- D.3 Implementing Finite-State Machine Control 1094
- D.4 Implementing the Next-State Function with a Sequencer 1108
- D.5 Translating a Microprogram to Hardware 1114
- D.6 Concluding Remarks 1118
- D.7 Exercises 1119
Appendix E. Survey of Instruction Set Architectures 1120
- E.1 Introduction 1121
- E.2 A Survey of RISC Architectures for Desktop, Server, and Embedded Computers 1122
- E.3 The Intel 80x86 1148
- E.4 The VAX Architecture 1168
- E.5 The IBM 360/370 Architecture for Mainframe Computers 1187
- E.6 Historical Perspective and References 1193
- Acknowledgments 1193
- References 1193
Glossary 1195
Further Reading 1209

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Afiljacja autora

David A. Patterson: Pardee Professor of Computer Science, Univers
John L. Hennessy: President, Stanford University, Palo Alto, CA

The Hardware/Software Interface

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